Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone

ABSTRACT

An apparatus and method for forming an insulated gate field effect device including a first conductivity-type semiconductor substrate having a concave with a curved surface formed on the main surface, an insulating film formed on the major surface including the concave, a first and second impurity regions of a second conductivity-type formed in the vicinity of the main surface at one side and the other side of the concave, respectively, and a conductive layer formed on the channel region which is formed along the concave between the first and second impurity regions with the insulating film interposed therebetween. The method includes forming a concave with the curve surface on the main surface of a semiconductor substrate; forming an insulating film on the main surface, forming a conductive layer above the concave with an insulating film interposed therebetween; forming a first and second impurity regions of a second conductivity type in the vicinity of the main surface at one side and the other side of the concave.

This application is a continuation of Ser. No. 07/660,522 filed Feb. 25,1991, now abandoned.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Japanese Patent Application SerialNo. 02-47100, filed Feb. 26, 1990, inventor Shinichi Sakamoto.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to insulated gate field effect devices,and more particularly, to achievement of a longer effective channellength without increasing the occupying area for insulated gate fieldeffect devices and a method of forming the same.

2. Description of the Related Art

As the high integration of semiconductor integrated circuit devices (IC)make progress, various problems arise. In insulated gate field effectdevices, the following problems caused by the high integration arenoted.

FIG. 6 is a sectional view showing a structure of a conventional planarinsulated gate field effect device. A MOS transistor is indicated inthis figure. Referring to FIG. 6, the MOS transistor comprises a n typesemiconductor substrate e.g. a n type silicon substrate 6, a p+ source 4and a p+ drain 5 each formed in the vicinity of the main surface ofsemiconductor substrate 6 by diffusion, a gate oxide film 22 formed onthe main surface of substrate 6, and a conductive layer formed above themain surface of substrate 6 with an insulating film 22 interposedtherebetween, i.e., a gate 21. A channel region 27 which is indicated by"x" in the figure is formed in the vicinity of the main surface betweenthe source 4 and the drain 5. Since the length of the channel regionwill be slightly corroded by a diffusion for the formation of the source4 and the drain 5, an effective channel length Le1 is obtained inpractice.

FIG. 7 is a structural sectional view showing the development of adepletion layer in the MOS transistor of FIG. 6. Referring to FIG. 7,the source 4 and the drain 5 are grounded to make definite thedevelopment of a depletion layer. Accordingly, a depletion layer 29 isformed so as to surround the source 4 and the drain 5.

In addition, voltage V_(G) is supplied to the gate 1 causing a depletionlayer 20 with a trapezoid configuration to be formed under the gate 1and between the depletion layers 29. In this case, the effective channellength Le1 is defined by the longer side of the trapezoid depletionlayer 20. Substrate voltage V_(sub) is supplied to the substrate 6.

FIG. 8 is a structural sectional diagram of the structure in FIG. 7 whenseen from the arrow 8. Referring to FIG. 8, a depletion layer 20 havingan effective channel width of We1 is formed between local oxidation ofsilicons (referred to as LOCOS hereinafter) 11 for element isolation.

PROBLEMS TO BE SOLVED BY THE INVENTION

FIG. 9 is a structural sectional view showing the status when operatingvoltage is supplied to the MOS transistor of FIG. 6. Referring to FIG.9, voltage V_(D) is supplied to the drain 5, and voltage V_(G) issupplied to the gate 1. The source 4 is grounded. It is seen from FIG. 9that the length of channel region 13 retracts from the drain 5 when theoperating voltages V_(D) and V_(G) are supplied. In other words, betweenone end of the channel region 13 and the drain 5, there is a region of alength Lg1 without a channel being formed therein. This means that fieldconcentration will occur in the vicinity of the main surface of thedepletion layer 20 near the drain 5.

This field concentration will cause the following several problems.First, breakdown voltage will occur in the vicinity of the drain due toits field concentration resulting in current to flow into the substrate6. This means that a greater voltage cannot be supplied to the gate 1and the drain 5. In addition, electrons (hot electrons) accelerated byfield concentration will flow into the gate oxide film 22 to causedegradation in withstand voltage of the gate oxide film 22. Summarizingthe above description, it is pointed out that the voltage that can besupplied to the drain 5 (the drain withstand voltage) and the voltagethat can be supplied to the gate 21 (the gate withstand voltage) aredegraded.

Furthermore, since the depletion layer 20 has a trapezoid configurationas shown in FIG. 9 (this phenomenon is called "fringe effect"), it isalso noted that the current is not increased in proportion to the lengthof the gate. Ideally, the current flowing between the drain and thesource increases in proportion to the length of the gate in an insulatedgate field effect device. However, the above-mentioned fringe effectwill hinder the proportional increase of the current. That is to say, asthe channel length shortens, threshold voltage Vt decreases. Therefore,subthreshold current will flow to the source 4 from drain 5 when thetransistor should be turned off.

The invention was made to solve the above problems, and has an object toobtain a longer effective channel length without increasing theoccupying area in an insulated gate field effect device.

SUMMARY OF THE INVENTION

An insulated gate field effect device in accordance with the presentinvention comprises a first conductivity type semiconductor substratehaving a concave with a curved surface formed on the main surface, aninsulating film formed on the major surface including the concave, firstand second impurity regions of a second conductivity type formed in thevicinity of the main surface and at one side and the other side of theconcave respectively, and a conductive layer formed on the channelregion which is formed along the concave between the first and secondimpurity regions with the insulating film interposed therebetween.

A method of forming an insulated gate field effect device in accordancewith the present invention comprises the steps of forming a concave witha curved surface on the main surface of a semiconductor substrate,forming an insulating film on the main surface including the concave,forming a conductive layer above the concave with an insulating filminterposed therebetween, forming first and second impurity regions of asecond conductivity type in the vicinity of the main surface and at oneside and the other side of the concave. Function

An insulated gate field effect device in accordance with the presentinvention has a channel region formed along a concave to obtain a longereffective channel length without an increase in the occupying area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of the structure of a MOS transistor showingan embodiment of the invention.

FIG. 2 is a structural sectional view showing the development of adepletion layer in the MOS transistor of FIG. 1.

FIG. 3 is a sectional structure view of the structure in FIG. 2 whenseen from a different direction.

FIG. 4 is a structural sectional view of the state when operatingvoltages are supplied to the MOS transistor of FIG. 1.

FIGS. 5A-5E are processing diagrams showing the formation of the MOStransistor of FIG. 1.

FIG. 6 is a sectional view showing the structure of a conventional MOStransistor.

FIG. 7 is a structural sectional view showing the development of adepletion layer in the MOS transistor of FIG. 6.

FIG. 8 is a structural sectional view of the structure in FIG. 7 whenseen from a different direction.

FIG. 9 is a structural sectional view showing the state when operatingvoltages are supplied to the MOS transistor of FIG. 6.

In the figures, 1 is the gate, 2 is the gate oxide film, 4 is thesource, 5 is the drain, 6 is the semiconductor substrate, 7 is thechannel region, 9 and 10 are the depletion layer, Le1 and Le2 are theeffective channel lengths.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a sectional view of a structure of an insulated gate fieldeffect device showing an embodiment of the invention. In this figure, aMOS transistor is indicated by way of an example. Referring to FIG. 1,the MOS transistor comprises a semiconductor substrate having a concavewhich is formed as a smooth curve, i.e., a silicon substrate 6, a source4 and a drain 5 formed on one side and the other side of the concave bydiffusion respectively, a gate oxide film 2 formed on the main surfaceof the substrate 6 including the concave, and a conductive layer formedon the concave, i.e., a gate 1. A channel region 7 is formed along theconcave between the source 4 and the drain 5 to obtain an effectivechannel length Le2 that is longer than the effective channel length Le1shown in FIG. 6.

FIG. 2 is a structural sectional view showing the development of adepletion layer in the MOS transistor of FIG. 1. Referring to FIG. 2, asource 4 and a drain 5 is provided to facilitate the development of thedepletion layer. A depletion layer 9 is formed below the source 4 andthe drain 5. Also, a depletion layer 10 is formed along the concavebetween the source 4 and the drain 5. When gate voltage V_(G) issupplied, a channel region is formed in the depletion layer 10 along theconcave.

FIG. 3 is a structural sectional view of the structure in FIG. 2 whenseen from the direction of the arrow 3. Referring to FIG. 3, a depletionlayer 10 is formed between LOCOS 11 along the concave when gate voltageV_(G) is supplied. A channel region 12 having the effective channelwidth We2 is formed along the concave in the depletion layer 10.

FIG. 4 is a structural sectional view showing the status when operatingvoltages are supplied to the MOS transistor of FIG. 1. The MOStransistor of FIG. 4 has the same operating voltages shown in FIG. 9,that is, has gate voltage V_(G) and drain voltage V_(D) supplied. Bycomparing FIG. 4 to FIG. 9, it can be seen that the two MOS transistorshave the same occupying area, except that the distance Lg2 between theend of channel region 12 and the drain 5 is longer than the distance Lg1indicated in FIG. 9. That is to say, since the effective channel lengthLe2 shown in FIG. 1 is longer than the effective channel length Le1shown in FIG. 6, the field concentration in the vicinity of the drain isreduced as compared with that of the MOS transistor in FIG. 6.

With the decrease of field concentration in the vicinity of the drain,electrons (hot electrons) accelerated by field concentration isprevented from flowing to the substrate 6 or the gate oxide film 2.Since the current flow to substrate 6 caused by voltage breakdown can beprevented, the degradation of the voltage to be supplied to the drain(the drain withstand voltage) may be avoided. In addition, thedegradation of the voltage to be supplied to the gate oxide film 2 (thegate withstand voltage) may also be avoided.

Furthermore, a strip depletion layer 10 is formed along the concave asshown in FIGS. 2 and 4, resulting in a current flow which isproportional to the gate length. In conventional MOS transistors, adepletion layer 10 having a trapezoid configuration as shown in FIGS. 7and 9 due to fringe effect is formed. On the contrary, a strip depletionlayer 10 as shown in FIGS. 2 and 4 according to the present invention isobtained. Consequently, the effect of a short or a long effectivechannel length is reduced.

In addition, the variation of threshold voltage Vt caused by thevariation of the supplied gate voltage can be prevented. As a result,the generation of the sub threshold current may also be avoided.

FIGS. 5A-5E are diagrams showing the process of forming the MOStransistor of FIG. 1. Firstly, as shown in FIG. 5A, an oxide film 2 isformed on a silicon substrate 6, followed by the formation of apatterned resist 21 on the oxide film 2. Then, as shown in FIG. 5B, anisotropic etching such as plasma etching or focal ion beam (hereinafterreferred to as EB) from above is performed to form a concave on thesubstrate 6. By removing the resist 21 and the oxide film 2, a siliconsubstrate 6 having a concave formed as shown in FIG. 5C is obtained.

Next, as shown in FIG. 5D, an new oxide film 2' is formed on thesubstrate 6 including the concave portion, and a conductive layer 1 forconstituting a gate, is formed at the concave portion of the new oxidefilm 2'. By implanting boron ions B+ from above into the substrate 6 tobe diffused with thermal process, the MOS transistor shown in FIG. 5E,i.e. an insulated gate field effect device having the structure shown inFIG. 1 is obtained.

In the MOS transistor shown in FIG. 1, the depth of the concave formedin the vicinity of the main surface of the substrate 6 is preferably setto the same value of the depth of the source 4 and the drain 5. Theeffect of the embodiment of this invention is most significant when thedepth of the concave is set to a value which ranges between the depth ofthe source 4 and the drain 5 and its twofold. That is to say, when thedepth of the drain is 0.5-0.6 μm, the depth of the concave is set to amaximum of approximately 1.0 μm. The effective channel length will bedesigned to lie within the range of 0.5 to 1.0 μm, resulting in theachievement of a 0.7 to 1.4 μm effective channel length in practice.

The configuration of the concave should preferably be smooth towards thedirection of the drain 5 from the source 4. In other words, it ispreferable to form a concave which is comprised of a curved surface.This is because if a concave which does not have a smooth configurationis formed, field concentration will occur at that portion.

EFFECT OF THE INVENTION

In accordance with the present invention, a channel region is formedalong a concave between first and second impurity regions to obtain aninsulated gate field effect device having a longer effective channellength without increasing the occupying area.

What is claimed is:
 1. An insulated gate field effect devicecomprising:a first conductivity type semiconductor substrate having amain surface; said semiconductor substrate having a concave surfaceformed on said main surface extending to a prespecified depth below themain surface; an insulating film formed on said concave surface; aconductive gate electrode formed above said insulating film, overlyingthe concave surface; first and second impurity regions of a secondconductivity type respectively formed in the substrate, in the vicinityof said main surfaces, self-aligned to and positioned at one side andthe other side of said gate electrode respectively; and a firstconductivity type region located in said semiconductor substrate betweensaid first and second impurity regions for defining a channel region anda channel-free region extending conformably under and along said concavesurface; wherein the depth of said concave surface is set to a valuewhich ranges between one and two times the depth of said first andsecond impurity regions, and wherein the concave surface is continuouslycurved in the vicinity of at least one of the first and second impurityregions to produce smooth merger of a conforming first depletion regionformed around the at least one impurity region and a conforming seconddepletion region formed in the vicinity of the gate electrode so thatexcessive field concentration will not develop in the vicinity where thefirst and second depletion regions meet.
 2. An insulated gate fieldeffect device according to claim 1, wherein one of said first and secondimpurity regions constitutes a drain region of said insulated gate fieldeffect device, the other of said first and second impurity regionsconstitutes a source region and wherein the concave surface iscontinuously curved at least in the vicinity of the drain region, wherethe channel-free region develops during an off state of the device, toproduce smooth merger of the conforming first depletion region whichdevelops in the vicinity of the channel-free region and the drain regionand the conforming second depletion region formed in the vicinity of thegate electrode so that excessive field concentration will not develop inthe vicinity of the channel-free region.
 3. An insulated gate fieldeffect device according to claim 1, which comprises a metal oxidesemiconductor (MOS) transistor, and wherein said insulating filmcomprises an oxide film.
 4. An insulated-gate field effect transistorcomprising:a substrate having a substantially planar main surface and aconcave surface portion extending continuously from the main surface toa predetermined depth below the main surface; an insulating layerconformably disposed on the main surface and the concave surfaceportion; a gate conformably disposed on the insulating layer, overlyingthe concave surface portion, the gate having opposed first and secondsides; implanted source and drain regions disposed within the substrateand self-aligned to the respective first and second opposed sides of thegate; and a channel-region formed between the source and drain regions,for defining a channel that conducts current between the source anddrain regions when the transistor is in a turned-on state; wherein achannel-free zone develops in the substrate, under the gate and betweenthe source and drain regions, when the transistor is in a turned-offstate; and wherein the gate and concave surface portion are curved atleast in the vicinity of the channel-free zone such that a smoothlycurved depletion zone boundary will develop in the vicinity of thechannel-free zone when the transistor is in the turned-off state.
 5. Aninsulated-gate field effect transistor according to claim 4 wherein theconcave surface portion is curved in a transverse cross-sectional planeextending through the transistor between but not intersecting the firstand second sides of the gate so as to provide an effective channel widthgreater than a width of the channel as projected onto the plane of themain substrate surface.
 6. An insulated-gate field effect transistoraccording to claim 5 wherein the concave surface portion is curved bothin the transverse cross-sectional plane and in a non-transversecross-sectional plane, extending between and joining the first andsecond sides of the gate, so as to provide an effective channel surfacearea greater than an area of the channel as projected onto the plane ofthe main substrate surface.
 7. An insulated-gate field effect transistoraccording to claim 6 wherein the concave surface portion is equallycurved both in the transverse cross-sectional plane and in thenon-transverse cross-sectional plane, so as to provide a sheet-likedepletion region having a uniform thickness and a smooth bottom boundaryunderlying the channel region and the source and drain regions, when thetransistor is in a turned-off state.
 8. An insulated-gate field effecttransistor according to claim 4 wherein the concave surface portion iscontinuously curved from the point where it descends below and away fromthe main surface of the substrate to the point where it ascends tore-join the main surface of the substrate.
 9. An insulated-gate fieldeffect transistor according to claim 4 wherein the gate fills the voidcreated by the concave surface portion and insulating layer at leastfrom the level where the concave surface portion and insulating layerdescend below the level of the main surface of the substrate.
 10. Aninsulated-gate field effect transistor according to claim 4 wherein theconcave surface portion is defined by isotropic plasma etching.
 11. Aninsulated-gate field effect transistor according to claim 4 wherein thedepth of the concave surface portion is set to a value which rangesbetween one and two times the depth of the source and drain regions. 12.An insulated-gate field effect transistor according to claim 4 whereinthe depth of the drain region is 0.5 to 0.6 microns and the depth of theconcave surface portion is set to approximately one micron.
 13. Aninsulated-gate field effect transistor according to claim 4 wherein theconcave surface portion is defined by focal ion beam etching.
 14. Aninsulated-gate field effect transistor comprising:a substrate having asubstantially planar main surface and a concave surface portionextending continuously from the main surface to a predetermined depthbelow the main surface; an insulating layer conformably disposed on themain surface and the concave surface portion; a gate conformablydisposed on the insulating layer, overlying the concave surface portion,the gate having opposed first and second sides; implanted source anddrain regions disposed within the substrate respectively at the firstand second opposed sides of the gate, the drain region having a bottomsurface which curves upwardly toward the top surface of the substrate;and a channel-region formed between the source and drain regions, fordefining a channel that conducts current between the source and drainregions when the transistor is in a turned-on state; wherein achannel-free zone develops in the substrate, under the gate and betweenthe source region and the upwardly curved bottom surface of the drainregion, when the transistor is in a turned-off state; and wherein thegate and concave surface portion are curved at least in the vicinity ofthe channel-free zone, and the upwardly curved bottom surface of thedrain region is also curved, such that a smoothly curved depletion zoneboundary will develop in the vicinity of the channel-free zone when thetransistor is in the turned-off state.